One class of integrated circuit memory devices includes NAND-type flash memory devices. FIG. 1 illustrates a timing diagram applicable to a conventional NAND-type flash memory device. In particular, FIG. 1 illustrates the timing of a clock enable signal (CLE), an active low chip enable signal (nCE), an active low write enable signal (nWE), an address latch enable signal (ALE), an active low read enable signal (nRE), bus signals (I/Ox) and a control signal R/nB during a memory read operation. To initiate this read operation, a read command (shown as “00h”) is received on the I/Ox bus. This read command is followed by a column address (CA1, CA2), a row address (RA1, RA2 and RA3) and a sensing command (shown as “30h”), which are all synchronized with the active low write enable signal nWE (having a period equal to tWC). The column address and the row address are received while the address latch enable signal ALE is active. A data sensing operation is performed during the interval tR. During this interval, the control signal R/nB remains low to reflect a busy condition and sensed data from a selected row is latched. After the time interval tRR, the read enable signal nRE switches low to an active level and the latched read data is produced onto the I/Ox bus. The switching of the read enable signal nRE from low-to-high enables a memory controller (not shown) to receive the data from the I/Ox bus. These and other aspects relating to the timing of a read operation within a memory device are more fully disclosed in U.S. Pat. No. 6,140,635, the disclosure of which is hereby incorporated herein by reference. The period of the read enable signal nRE, which is illustrated as a read cycle time tRC, may vary depending on application. Unfortunately, if the read cycle time tRC becomes excessive, parasitic leakage currents and charge sharing may occur on the data lines providing the read data and read errors may occur.